In this new technical article, I will present how central elements like the ST bus, memory and clocks are implemented in zeST. This is a crucial part, since the choices we make here constrain all the rest of the hardware implementation. These choices are also very dependent from the hardware platform we are working on. I will try to explain in the most understandable way as I can, so anyone with very basic notions of synchrorous logic and timing should be able to understand.

This rather technical post describes how floppy drive emulation has been implemented in zeST. I will try to explain about some internals of the ST, and the technical choices I made to implement floppy functionality that would work as similarly as possible to the real hardware. The ST architecture around floppy disk management Here is an overview of the different main components of the Atari ST that are responsible for managing the floppy drive:

After some weeks of reading the HDMI documentation, programming, debugging, some months of inactivity because I was very busy with my job, and after an active debugging session at Silly Venture 2K21 in Gdańsk, Poland, I finally got the HDMI output in working order on the Microphase Z7-Lite FPGA board. There should have been a video here but your browser does not seem to support it. A HDMI transmitter with the required functionality The challenge was to address the HDMI port on a board that had no dedicated HDMI controller chip, so the controller had to be implemented in the FPGA logic.

As I explained in the previous post, I have acquired a Microphase Z7-Lite board, in order to check if it could be used as a possible platform for zeST. As it is currently taking most of my time on zeST development, I am writing this post so you can understand what I am doing at the moment. Meet the Microphase Z7-Lite board It is the cheapest I could find with the required elements I need: A Xilinx Zynq-7000 FPGA SoC, a SD card slot, sufficient memory, a HDMI port and some USB connectivity.

Current status of zeST I’m taking profit from this new website to summarize the current status of the zeST project. Target platform The zeST project is based on the Xilinx Zynq-7000 family of FPGA-based SoCs, with a FPGA, a two-core 32-bit ARM CPU, and a number of hardware controllers, all that in a single chip. For the moment, I am working on a MyIR Z-Turn board, whose availability seems to be decreasing with time, so I’m looking for a replacement board that would serve as the new reference board.