Here comes a new release with performance improvements and useful improvements on the software side. Turbo mode optimisation There has been a pass of optimisations in the memory accesses in Turbo mode. The two wait cycles on reads are gone, and read burst management has had its latency reduced by a few cycles. Performance has therefore improved, as you can see on the new results: The average peformance is now 540% of that of a real ST, which is 28% faster than the previous release of zeST (420%).

This new release adds major improvements, that I describe in this article. Turbo mode zeST now has a turbo mode, allowing the 68000 CPU to run at 50 MHz, instead of the original 8 MHz. Of course the goal of turbo mode is no longer cycle exactness, but rather achieve the maximum possible available performance allowed by your FPGA hardware. Switch turbo mode off, and you’re back to cycle exact 8 MHz again.

Here is the new release of zeST, mostly with fixes to make life better. Scan doubler rework The scan doubler has received particular attention for this new release. Indeed, a large part of its logic has been rewritten. This module is one of the first implemented in zeST, even before I got the TOS system to boot. It was already there when I displayed my first image out of the Atari ST logic on a HDMI screen.